#Ripple counter timing diagram plus#

Instead, the total response time of a synchronous counter like the one in Figure1( c ) is the time it takes one FF to toggle (FF t pd ) plus the time for the new logic levels to propagate through a single AND gate(AND gate t pd ) to reach the J, K inputs. Thus, unlike the asynchronous counters, the propagation delays of the FFs do not add together to produce the overall delay. In a parallel counter, all of the FFs will change states simultaneously that is, they are all synchronized to the NGTs of the input clock pulses. Advantage of Synchronous Counters over Asynchronous Counters By connecting the logic signal ABC to FF D’s J and K inputs, this FF will toggle only when A = B = C = 1.įigure1(d): Timing diagram of 4-bit (MOD-16) Synchronous UP counter using J-K flip-flop. When the count is 0111, the next NGT must toggle D to the 1 state when the count is 1111, the next NGT must toggle D to the 0 state. In a like manner, we can see that flip-flop D must toggle on each NGT that occurs while A = B = C = 1. By connecting the logic signal AB to FF C’s J and K inputs, this FF will toggle only when A = B = 1.

For example, when the count is 0011, the next NGT must toggle C to the 1 state when the count is 0111, the next NGT The counting sequence shows that flip-flop C must change states on each NGT that occurs while A = B = 1. This operation is accomplished by connecting output A to the J and K inputs of flip-flop B so that J = K = 1 only when A = 1. The counting sequence shows that flip-flop B must change states on each NGT that occurs while A = 1.įor example, when the count is 0001, the next NGT must toggle B to the 1 state when the count is 0011, the next NGT must toggle B to the 0 state and so on. For this reason, its J and K inputs are permanently HIGH so that it will toggle on each NGT of the clock input. The counting sequence shows that flip-flop A must change states at each NGT. Let’s look at the counting sequence in Figure1(a) to see what this means for each FF. Circuit Operation of a 4-bit ( MOD-16) synchronous counterįor a 4-bit ( MOD-16) synchronous counter circuit, to count properly on a given NGT (negative transition) of the clock, only those FFs that are supposed to toggle on that NGT should have J = K = 1. That is counter recycles after 16 clock pulses.įigure 1(a): counting sequence in Synchronous MOD-16 counter. The synchronous counter requires more circuitry than does the asynchronous counter.The J, K inputs of the other FFs are driven by some combination of FF outputs. Only flip-flop A, the LSB, has its J and K inputs permanently at the HIGH level.The CLK inputs of all of the FFs are connected together so that the input clock signal is applied to each FF simultaneously.If we see the circuit arrangement for this synchronous counter ( Figure1(a)), we will find out the following points: This is accomplished by using the J and K inputs and is illustrated in Figure1(c) for a 4-bit, MOD-16 synchronous counter. Design steps of 4-bit synchronous counter (count-up) using J-K flip-flopĪs the input clock pulses are applied to all the Flip-flops in a synchronous counter, some means must be used to control when an FF is to toggle and when it is to remain unaffected by a clock pulse. These limitations can be overcome with the use of synchronous or parallel counters in which all of the FFs are triggered simultaneously (in parallel) by the clock input pulses. The FFs do not all change states simultaneously in sync with the input clock pulses. The problems encountered with ripple counters are caused by the accumulated FF propagation delays. Why are we going for synchronous counter instead of asynchronous counter? For example, a 4-bit counter has 24=16 different states (0 to 15) and is known as the MOD-16 counter. We know that n-bit synchronous counters can count N = 2n clock pulses, Where n = Number of Flip Flops. For example, in a 3-bit up-counter the counting sequence is 0,1,2,3,4,5,6, and 7 Why is the 4-bit counter known as MOD-16 counter? In a count-up mode, the counter value sequentially increased. Synchronous binary counters can be able to count either in increasing or decreasing order. Therefore, the same clock pulse simultaneously triggers all flip-flops of the counters. In a synchronous counter, the clock input terminals of all flip-flops are commonly connected. Related posts (for further study) on Binary Counter.Advantage of Synchronous Counters over Asynchronous Counters.The basic principle for constructing a synchronous counter can therefore be stated as follows.Circuit Operation of a 4-bit ( MOD-16) synchronous counter.Design steps of 4-bit synchronous counter (count-up) using J-K flip-flop.Why are we going for synchronous counter instead of asynchronous counter?.Why is the 4-bit counter known as MOD-16 counter?.

Ripple counter timing diagram